Siemens Digital Industries Software, a unit of Siemens AG, on Monday said it launched new software called Tessent Multi-die that automates a design process for testing chips made with advanced packaging.
While chips have traditionally been packaged with one silicon tile inside, as the industry faces challenges making features on these tiles smaller and smaller to cram more computing power into them, companies including Intel are starting to stack several of them, sometimes mixing and matching different technologies, to improve performance.
But testing these chips after they are made has been difficult as there are several layers of tiles, and Siemens’ head of the Tessent business Ankur Gupta said until now Siemens has had to work with customers on a case-by-case basis.
Testing is a key part of the chip-making process and a port to test them has to be designed into the chip before they are made.
“What we are doing now is taking all of those learnings and automating the solution, making it available general purpose for everybody to use,” Gupta told Reuters.
He said making the testing process easier for chips with advanced packaging, also referred to as 2.5 and 3-dimensional packaging, will help give the new technology a boost.
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